Simplify your timing designs with low power jitter attenuators

Don’t be afraid of multiple timing domains and challenging frequencies. Because it doesn’t have to be challenging. We make your timing design simple.

The insatiable demand for bandwidth to support applications such as video streaming and cloud computing is driven telecom service providers to continuously increase network capacity and migrate to higher speed Internet Infrastructure equipment. Theses industry trends and the overall market pressure to reduce optical transmission and switching cost-per-bit significantly increase the need for highly integrated, high-performance, frequency-flexible clocks that are easily reconfigurable cross a broad range of applications.

Simplified Clock Generation in OTN and 10/40/100G Ethernet

Next-generation 10/40/100G OTN switching and transmission equipment used in Internet Infrastructure is transitioning to higher port densities to further scale network capacity. This evolution to higher-speed equipment is driving the market need for more highly integrated physical-layer timing devices that provide multiple independent phase-locked loops (PLLs) in a single IC, minimizing the PCB footprint in tightly packed, high-density line cards.

DSPLL® Technology

Silicon Labs invented DSPLL® technology – a hybrid approach combining digital signal processing (DSP) and PLL techniques — to simplify the clock multiplication and jitter attenuation circuitry required in high-speed Internet Infrastructure applications. Now in its fourth generation, this advanced, patented timing technology is now the best available solution for replacing multiple discrete PLL components with a single IC that integrates DSP circuitry and an ultra-low-jitter clock or voltage-controlled oscillator.

DSPLL_BD

Our latest DSPLL architecture is compact and scalable, making it possible to build monolithic, single-chip multi-PLL jitter attenuating clocks that are significantly smaller and lower jitter than competing solutions. Conventional solutions use a digital PLL (DPLL) for jitter attenuation and an analog PLL (APLL) for frequency translation. This legacy architecture is not optimized for space, power or performance. Because each APLL uses a discrete VCO, the traditional architecture is highly-susceptible to crosstalk when the VCOs are operating in close frequency proximity.

In contrast, Silicon Labs’ DSPLL architecture replaces both the DPLL and APLL, provides the highest level of PLL integration and performance in the industry. DSPLL technology leverages a highly-digital, low-noise architecture to deliver a solution that is highly optimized for space and power. Each DSPLL is isolated using an extensive number of on-chip regulators, providing noise isolation while minimizing susceptibility to crosstalk. As a result, a DPLL-based timing device, such as an Si534x jitter attenuator, delivers any-frequency clock synthesis with greater than 60 percent lower jitter and a 50 percent smaller footprint than comparable multi-PLL solutions.

DSPLL

For frequency control products such as crystal oscillators (XOs), DSPLL technology eliminates numerous complex manufacturing steps required to frequency tune traditional SAW and crystal-based implementations by moving the frequency synthesis capability into a high-performance, mixed-signal IC. Silicon Labs’ XOs and VCXOs derive frequencies up to 1.4 GHz from a simple, low-frequency resonator and calibrate the output to an initial accuracy of 1 ppb. The use of a low-frequency crystal provides tremendous improvements in aging, temperature stability and mechanical reliability.

Download the white paper, Innovative DSPLL ® and MultiSynth clock architecture enables high-density 10/40/100G line card designs, to learn more.

Ask your question about our Timing solution on our community.

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