Three reasons why clock designers choose Si534x Jitter Attenuators

With the increase in usage of connected devices and cloud services, users demand new and diverse services for various Internet content such as video streaming, mobile news feed and data storage. The data services require many different clocks, causing challenges for clock tree designers to make Internet Infrastructure (II) applications simpler, faster and more reliable.

The Si534x Jitter Clock Family is designed to help the designers meet the high performance and ease-of-use requirements of the II applications. Let’s take a look at three main reasons why clock designers choose Si534x Jitter Attenuators over competing products.

Reason 1. Any frequency without compromise 

FPGA, ASIC, and PHY all require a diverse mix of frequencies and formats for varied services like edge routers, storage, servers, and switches. In a conventional approach, a jitter clock family only supports specific frequencies on a specific output. The Si534x Jitter Clocks offer industry-leading flexibility by generating any combination of frequencies on any output with no compromise on phase jitter performance.


Reason 2. Best-in-class integration

MultiSynth generates any combination of frequencies, and it enables single IC clock trees without the need for many discrete components. The clock tree-on-a-chip integration reduces the bill of materials (BOM) cost and simplifies clock design.

Reason 3. Intuitive ClockBuilder Pro software

We also provide ClockBuilder Pro for a quick and easy evaluation. With ClockBuilder Pro, clock designers can create an optimized custom clock in minutes. ClockBuilder Pro validates your frequency plan, measures clock performance and generates orderable part numbers automatically so that designers can get factory customized samples in 2 weeks.

Do you want to learn more about the Si534x jitter clocks? View the following presentation: 

Click to visit the Si534x product page 

If you have any questions about the Si534x family, visit our community

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