Don’t be afraid of multiple timing domains and challenging frequencies. Because it doesn’t have to be challenging. We make your timing design simple.
Silicon Labs has developed a new portfolio of clock generators and jitter attenuators optimized for high-speed, frequency-flexible, ultra-low-jitter clock synthesis. These clock devices enable system designers to design “any-port, any-protocol” line cards with industry-leading jitter performance of < 100 fs RMS typical (12 kHz to 20 MHz). The devices also support “on-the-fly” frequency reconfiguration. This feature dramatically simplifies system design, enabling significantly lower cost and more flexible service provisioning in SDN environments. Service provisioning allows network operators to respond to users’ rapidly-changing demands for diverse voice, video and data services, such as cloud storage, video streaming and mobile services.
Si534x – Ultra-low jitter, frequency flexible timing solutions from Silicon Labs
Si5345/44/42 Jitter Performance
The jitter measurements in Table 1 show typical jitter performance when the Si5345/44/42 is configured for a typical 10/40/100G OTN application. The Si534x provides highly-consistent, repeatable ultra-low-jitter performance across process, voltage and temperature.
Fourth-Generation DSPLL Enables High Port Density Line Cards
Next-generation 10/40/100G OTN switching and transmission equipment is transitioning to higher port densities to further scale network capacity. This is increasing the market need for more highly integrated physical-layer timing devices that provide multiple independent PLLs (Phase-Locked Loops) in a single IC, minimizing the PCB footprint in tightly packed, high-density line cards.
The fourth-generation DSPLL architecture is compact and scalable, making it possible to build monolithic, single-chip multi-PLL jitter attenuating clocks that are significantly smaller and lower jitter than competing solutions. Figure 1 contrasts the Si5347 quad-DSPLL jitter attenuating clock with a conventional digital + analog phase-locked loop (DPLL + APLL) approach. Conventional solutions use a DPLL for jitter attenuation and an APLL for frequency translation. This architecture is not optimized for space, power or performance. Because each APLL uses a discrete VCO, the traditional architecture is highly-susceptible to crosstalk when the VCOs are operating in close frequency proximity.
In contrast, Silicon Labs’ DSPLL® architecture replaces both the DPLL and APLL. The DSPLL leverages a highly-digital, low-noise architecture to deliver a solution that is highly optimized for space and power. Each DSPLL is isolated using an extensive number of on-chip regulations, providing noise isolation while minimizing susceptibility to crosstalk. As a result, the Si5347 device delivers any-frequency clock synthesis with greater than 60 percent lower jitter and a 50 percent smaller footprint than comparable multi-PLL solutions. With this approach, the Si5347 provides the highest level of PLL integration and performance in the industry.
Figure 1. Quad-DSPLL Jitter Attenuating Clock vs. Conventional Multi-PLL Architecture
Download the white paper, Innovative DSPLL ® and MultiSynth clock architecture enables high-density 10/40/100G line card designs, to learn more.
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