What contributes to a clock distribution buffer’s additive phase noise performance, and how can you optimize performance without increasing costs? We’ll take a look a few key considerations.
If you’re working on clocks, you understand the importance of power supply decoupling and signal integrity. What you can sometimes overlook is that the input rise and fall time has a significant impact on additive phase jitter. While on first glance this is true, what makes the statement even more accurate is to consider both the amplitude versus rise and fall time, which is expressed as Volts/ns—or slew rate.
Calculating slew rate with digital or analog components
Most engineers would associate slew rate with analog components, such as an op-amp, and it’s uncommon to see a slew rate requirement in a digital component data sheet. Even though we’re still dealing with digital logic levels or inputs, slew is just a more accurate way to describe what can really improve or degrade additive phase jitter. Take for example a differential LVDS signal which has a 350 mV single ended amplitude and a 400 ps rise and fall time measured at 20% and 80%, the differential slew rate would be (2 x 350 mV x 0.6) / (400 ps) or 1.05 V/ns. For the purpose of this post only differential slew rate is used.
As an example shown in Table 1, note the additive jitter specification includes a description of slew rate, output frequency and output logic format as all have an effect on additive jitter.
A clock distribution IC does not generate a clock but rather regenerates and provides multiple copies. As such phase noise cannot be measured unless an input is applied and total jitter is measured—the clock buffer’s contribution is referred to as additive phase jitter. In order to characterize the phase jitter contribution due to the buffer, the source is first measured, then the source plus DUT is measured and finally phase jitter is calculated by using the following equation:
Note that when a clock buffer’s additive jitter and the source jitter number (usually given as an rms value) are provided, a root sum square value will be used to calculate total jitter:
How slew rate impacts jitter performance
It is important to know what factors will have an impact on the jitter performance when adding a distribution buffer to a clock tree. This is also very important when reading data sheets, as how the supplier specifies their buffer’s jitter performance can greatly impact the number you see in the data sheet. For example, two buffers with similar performance may show very different additive jitter specifications, if one vendor used a much faster slew rate than the other.
Figure 1 shows the additive phase jitter versus input slew rate for two different clock buffers. In both cases the additive jitter decreases or improves as slew rate increases. What is interesting are the results shown in red can appear to be overall better. However, it’s actually more sensitive and quickly degrades at lower slew rates, such as a low frequency sine wave or CMOS clock. This graph highlights the importance of comparing additive phase jitter using the same slew rate values.
There are many more considerations that come into play when you’re considering the cause of additive jitter in your buffers. For a full discussion of the causes and solutions to additive jitter, read the full application note here.